1. Field of the Invention
The field of the present invention relates to a nonvolatile semiconductor memory device and a manufacturing method therefor, and more particularly to an electrically programmable metal-oxide-semiconductor (MOS) type nonvolatile semiconductor memory device having an asymmetric source and drain and a manufacturing method therefor.
2. Description of Related Art
Flash memories are a growing class of nonvolatile storage integrated circuits. Flash memories have the capability of electrically erasing, programming, and reading a memory cell in the chip. A flash memory cell is formed using so-called floating gate transistors in which the data are stored in a cell by charging or discharging the floating gate. The floating gate is a conductive material, typically polysilicon, which is insulated from the channel of the transistor by a thin layer of oxide, or other insulating material, and insulated from the control gate or word-line of the transistor by a second layer of insulating material.
Data are stored in the memory cell by charging or discharging the floating gate. The floating gate is charged through a Fowler-Nordheim (FN) tunneling mechanism by establishing a large positive voltage between the gate and source or drain. This causes electrons to be injected into the floating gate through the thin insulator. Alternatively, an avalanche injection mechanism may be used by applying potentials to induce high energy electrons in the channel of the cell. The electrons are injected across the insulator to the floating gate. When the floating gate is charged, the threshold voltage for causing the memory cell channel to conduct is increased above the voltage applied to the word-line during a read operation. Thus, when a charged cell is addressed during a read operation, the cell does not conduct. The non-conducting state of the cell can be interpreted as a binary 1 or 0 depending on the polarity of the sensing circuitry.
The floating gate is discharged to establish the opposite memory state. This function is typically carried out by a FN tunneling mechanism between the floating gate and the source or the drain of the transistor, or between the floating gate and the substrate. For instance, the floating gate may be discharged through the source by establishing a large positive voltage from the source to the gate, while the drain is left at a floating potential.
A popular architecture for flash memories is the Divided NOR structure (DINOR) in which the drain of each cell is connected to a bit-line and the source of adjacent columns of cells share a bit-line. A drawback to the DINOR structure is that a cell which shares both a word-line and a bit-line with a cell being programmed, may be susceptible to a disturb condition arising from either FN tunneling or hot electron injection during programming. This results in an unacceptable memory loss.
The major challenge of flash memory design is to improve programming speed while maintaining disturb resistance. Traditionally, the disturb problem has been dealt with by providing asymmetric diffusions on the source and drain side of the cell. The drawback to these approaches is that they are not suitable for small scale memory arrays.
To realize further reductions in array size, it would be desirable to find new solutions to the disturb problems that do not involve the added complexity and space required by asymmetric bit-lines. What is needed is a way to increase programming speed and reduce the source disturbance at the same time.